A generic communication link comprises a transmitter, communication channel, and receiver. A Serializer—Deserializer (SerDes) receiver is an example of a device that processes analog signals transmitted through a channel, and the SerDes receiver typically includes components to compensate for impairments introduced by the channel. Such impairments typically include added noise and inter-symbol interference characterized by the transfer function of the communication channel.
A SerDes receiver includes equalization, for which the datapath typically includes a combination of a Continuous-Time Linear Equalizer (CTLE), a Feed Forward Equalizer (FFE), a Decision Feedback Equalizer (DFE), and various adaptation circuits employed to adapt the various equalizer and filter parameters. For a digital implementation of a SerDes receiver, clock frequencies available for datapath signal processing (DSP) and clock and data recovery (CDR) are an order of magnitude, for example, of 8-10 times the signal frequency, lower that in case of an analog equalization datapath. To maintain the data rate through the SerDes receiver, the digital implementation datapath is parallelized by the same factor (8-10 times). DFE implementations generally do not parallelize efficiently due a requirement of an immediate feedback from the previous bit to the next bit of processed data. To address this architectural feature in parallel implementations of the DFE, an unrolling technique may be used, but this unrolling technique yields prohibitively large designs for practical applications. Cost of implementing a multi-tap DFE solution is generally prohibitive in higher data rate applications because of the requirement of al-UI (unit interval) feedback in a non-unrolled implementation, or because of exponential growth in gate count and power in the case of parallel unrolled implementation.